1. Field of the Invention
The present invention relates to an isolation method and a method for manufacturing a semiconductor device using the same, more particularly to a shallow trench isolation method and method for manufacturing a non-volatile memory device using the same.
2. Description of the Related Art
In manufacturing a highly integrated memory device, the integration density of a memory cell is determined according to the layout of the memory cell and scalability of the layout, and depends upon the reduction of the critical dimension. As the critical dimension is reduced below sub-micron scale, the scalability of the layout is limited by the resolution of manufacturing process and alignment tolerance of the layout mask. The alignment of the mask is limited according to the technique used for mechanically placing the mask over a wafer and the technique used for forming a consistent pattern on the mask. If the alignment tolerance is accumulated, a misalignment error occurs in the array layout. Therefore, less reliance of alignment using a critical mask is preferable in order to control alignment tolerance on chip design. Therefore, a self-aligned process wherein the critical mask is not used has been developed.
Since highly-integrated memory design commonly requires an isolation structure between cells of a row direction in an array, it is preferable to minimize the dimension of the isolation structure in order to increase the integrity of the memory array. However, the size of the isolation structure is defined by the process for forming the isolation structure and the alignment of the memory array structure.
Generally, the isolation structure is formed using a thermal field oxidation process such as local oxidation of silicon (LOCOS). According to LOCOS isolation, a nitride film is patterned after forming an oxide film and a nitride film sequentially on a silicon substrate. Then, using the patterned nitride film as an oxidation prevention mask, a field oxide film is formed by selectively oxidizing the silicon substrate. According to LOCOS isolation, as oxygen penetrates into a side of the oxide film, a bird""s beak structure is generated at end portions of the field oxide film. This can lead to a decrease in the available length of the active region, and consequently, the electrical characteristics of the element are adversely affected.
For this reason, and others, in VLSI semiconductor devices, shallow trench isolation structures draw a great deal of attention. According to the shallow trench isolation process, a trench is formed by etching a silicon substrate and an oxide film is deposited in order to fill the trench. Then, a field oxide film is formed in the trench by etching the oxide film to remove those portions that are not part of the trench, for example, by an etch back process or a chemical mechanical polishing process.
The above-mentioned LOCOS method or shallow trench isolation method includes a mask process and a field oxide film forming process in order to define the isolation region. After forming an isolation structure, a mask process for forming memory cells is performed. Therefore, in view of the alignment tolerance when forming an isolation structure with respect to the alignment tolerance of the memory cell layout, a misalignment can occur that may critically affect operation of the resulting elements.
In addressing the above alignment problems, a method for forming a LOCOS isolation structure that self-aligns with the floating gate in a non-volatile memory device has been developed. Further, a method for forming a shallow trench isolation that self-aligns with a floating gate is disclosed in U.S. Pat. No. 6,013,551. The above methods provide for self-alignment between the active region and the floating gate because the floating gate and the active region that are used in storing electric charge are defined simultaneously using one mask.
Non-volatile memory devices, for example flash memory, offer the advantage of maintaining data state, even when power is removed. Since such devices find application in a range of products, demand for flash memory that enables electronic data to be inputted/outputted continues to increase.
Memory cells for storing data in flash memory device include a floating gate formed on a silicon substrate. A tunnel oxide film is interposed between the silicon substrate and the floating gate and a stack type gate structure of control gate is formed on the floating gate where a dielectric film is interposed between the floating gate and the control gate. In a flash memory device having the above-mentioned structure, data are stored by applying appropriate voltage to the control gate and the substrate to introduce electrons to the floating gate or to extract electrons from the floating gate. At this time, the dielectric film maintains an electric charge characteristic charged on the floating gate and transmits the voltage of the control gate to the floating gate.
FIG. 1A to FIG. 1E are cross-sectional views illustrating a conventional self-aligned shallow trench isolation method applied to non-volatile memory device.
Referring to FIG. 1A, an oxide film 11 having a thickness of 90 xc3x85 and a first polysilicon layer 13 having a thickness of 400 xc3x85 are deposited sequentially on a semiconductor substrate 10 such as a silicon substrate. The oxide film is provided for forming a tunnel oxide film, in other words for a gate oxide film of a memory cell, and the first polysilicon layer is provided for forming a floating gate.
A stopper layer 15 comprised of silicon nitride is formed on the first poly silicon layer 13 so as to have a thickness of 600 xc3x85, and then, a hard mask layer 17 comprised of oxide is formed on the stopper layer 15 so as to have a thickness of 500 xc3x85. An anti-reflection layer 19 is deposited on the hard mask layer 17 to have a thickness of 800 xc3x85.
Then, a photoresist pattern 22 is formed on the anti-reflection layer 19 in order to define an active region.
Referring to FIG. 1B, an anti-reflection layer pattern 20, a hard mask layer pattern 18, a stopper layer pattern 16 are formed by sequentially dry etching the anti-reflection layer 19, the hard mask layer 17 and the stopper layer 15 using the photoresist pattern 22 as an etching mask.
Referring to FIG. 1C, after removing the photoresist pattern 22 by an ashing or a stripping process, the first floating gate 14 and a gate oxide film 12 are formed by sequentially dry etching the first poly silicon layer 13 and the oxide film 11 using the hard mask layer pattern 18 as an etching mask.
Referring to FIG. 1D, a trench 24 is formed by etching the upper part of the substrate 10 adjacent to the first floating gate 14 to have a depth of 2300 xc3x85 using the hard mask pattern 18 as an etching mask. At this time, the anti-reflection layer pattern 20 is removed by etching.
Referring to FIG. 1E, a gap-fill oxide film 26 is formed using CVD method in order to fill the trench 24. Then, a field oxide film is formed in the trench 24 by removing the gap-fill oxide film 26 using CMP until the upper surface of the stopper layer pattern 16 is exposed.
In the case of a memory device to which the above described shallow trench isolation process is applied, as the design-rule decreases, the depth of the trench also decreases, which in turn can cause isolation failure. In order to prevent this failure, if the depth of the trench is increased, an aspect ratio of trench region becomes large and, consequently, voids occur during the gap-filling process.
An etching method using a photoresist mask and an etching method using a hard mask are generally used for forming a trench by etching. In case of the latter, as there is a limit to the degree that the thickness of the stopper layer composed of nitride can be decreased, trench etching is performed using a hard mask comprising oxide or silicon oxynitride. At this time, since the gap-fill oxide layer is deposited in such a state that the thickness of the hard mask layer on the stopper layer is 400 xc3x85, the aspect ratio of the trench region becomes greater. In addition, in such a structure that the first polysilicon layer for the floating gate exists under the stopper layer, the aspect ratio of the trench region increases greater and, as a result, voids occur during the gap filling process. In order to prevent the void occurrence, the aspect ratio is preferably made to be lower than 2.2. However, according to above-mentioned conventional methods, it is practically difficult to increase the trench depth by more than 2000 xc3x85. As a result, isolation failures commonly occur.
In order to address the above-mentioned limitations, it is a first object of the present invention to provide a shallow trench isolation method that can ensure the gap-filling margin of the trench.
It is a second object of the present invention to provide a method for manufacturing a non-volatile memory device that can ensure the gap-filling margin of the trench.
In order to achieve the first object of the present invention, there is provided a shallow trench isolation method wherein an oxide film is formed on a semiconductor substrate. After forming a stopper layer on the oxide film, a hard mask layer is formed on the stopper layer. A hard mask layer pattern, a stopper layer pattern and an oxide film pattern are formed via patterning the hard mask layer, the stopper layer and the oxide film. Then, a trench is formed by etching an upper portion of the substrate using the hard mask layer pattern as an etching mask. After removing the hard mask layer, a field oxide film is formed in the trench.
In order to achieve the second object of the present invention, there is provided a method for manufacturing a non-volatile memory device wherein an oxide film for a gate oxide film is formed on a semiconductor substrate. After forming a first conductive layer for a floating gate on the oxide film, a stopper layer is formed on the first conducing layer. A hard mask layer is formed on the stopper layer. A hard mask layer pattern and a stopper layer pattern are formed via patterning the hard mask layer and the stopper layer. After forming a first floating gate pattern and a gate oxide film by etching the first conductive layer and the oxide layer using the hard mask layer pattern as an etching mask, an active region of the substrate is defined by etching the substrate to form a trench aligned with the first floating gate pattern. After forming a trench aligned to the first floating gate pattern by using the hard mask layer pattern as an etching mask, the hard mask layer pattern is removed. A field oxide film is formed in the trench; and a dielectric film and a control gate layer are sequentially formed on the first floating gate pattern.
According to the present invention, since the hard mask layer which exists on the stopper layer is removed prior to deposit of the gap filling oxide film, an improved gap filling margin can be obtained by decreasing the aspect ratio of the trench region. Therefore, gap filling without voids can be accomplished and occurrence of an isolation failure can be prevented by increasing the depth of the trench.